Embodiments of the present invention relate to layout of a symmetrical circuit which may be used as a static random access memory (SRAM) cell, a sense amplifier, or other circuit where alignment tolerant balanced operation is important.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield require a finely tuned manufacturing process. Second order effects that might have been ignored a decade ago are now critical to cost-effective processing as will be explained in detail.
FIG. 1 is a diagram of a silicon semiconductor wafer of the prior art. The wafer has a uniform lattice structure of face-centered cubic crystals as indicated by circles 104, 106, 108, and 110. A notch 102 or flat indicates the crystal orientation of the wafer as defined by Miller indices. For example, a type <100> orientation includes equivalent directions [100] (116), [010] (112), [001], [−100], and [0-10]. A type <110> orientation includes equivalent directions [110] (114), [011], [101 ], [−1-10], [0-1-1], [−10-1], [−110], [0-11], [−101], [1-10], [01-1], and [10-1]. In general, crystal orientation may have a significant impact on transistor performance. Sayama et al., Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length, IEDM 99-657 27.5.1 (1999) discuss the effect of channel orientation on P-channel and N-channel transistors. A 2005 IMEC Channel engineering report (http://www.imec.be/wwwinter/mediacenter/en/SR2005/html/142274.html) agrees with these findings and discloses that N-channel transistors are less orientation dependent than P-channel transistors but may be affected by stress. In addition, Bryant et al. (U.S. Pat. No. 7,102,166, filed Apr. 21, 2005) disclose hybrid orientation of field effect transistors to reduce stress.
Referring to FIG. 2, there is a schematic diagram of a six-transistor (6-T) static random access memory (SRAM) cell of the prior art. The same reference numerals are used throughout the drawing figures to indicate common features. The memory cell includes P-channel drive transistors 220 and 222 and N-channel drive transistors 230 and 232 arranged in a cross-coupled configuration. The P-channel drive transistors are connected at power supply terminal Vdd 200. The N-channel drive transistors are connected at reference supply terminal Vss 202. The drain terminals of drive transistors 220 and 230 are connected to true sense terminal 240. Likewise, the drain terminals of drive transistors 222 and 232 are connected to sense terminal 242. Sense terminals 240 and 242 are selectively connected to true bit line 204 (BL) and complementary bit line 206 (/BL), respectively, by access transistors 208 and 210. These access transistors are controlled by signals applied to word line terminal 102 (WL). Crystal orientation and other factors may have a significant impact on 6-T memory cell performance such as static noise margin, trip voltage, disturb read and write, and other parameters as will be discussed in detail.